1. Field of the Invention
The present invention relates to a semiconductor device such as a nonvolatile memory in which a plurality of transistor elements are arranged, and to a method of fabricating such a device.
2. Description of the Related Art
Semiconductor devices of various configurations are currently in practical use, and in nonvolatile memory such as flash memory, EPROM, and EEPROM, transistor elements having floating gates (hereinbelow abbreviated as xe2x80x9cFGxe2x80x9d) are arranged in a two-dimensional form as memory cells. In this case, the FG of the transistor elements hold injected electrons, by which nonvolatile storage of binary data or multivalue data is realized.
This type of nonvolatile memory also has various modes, with the FN (Fowler-Nordheim) tunneling mode and CHE (Channel Hot Electron) mode as modes of writing/erasing. When erasing stored data in the AND flash memory of the FN tunneling mode, for example, electrons are drawn out from the FG of transistor elements, which are the memory cells; a voltage of xe2x88x9220 (V) is therefore applied to the control gate (hereinbelow abbreviated as xe2x80x9cCGxe2x80x9d) that confronts the FG, with the substrate as 0 (V). Thus, making the confronting areas of FG and CG greater than the confronting areas of the FG and channel and increasing the capacitance enables a reduction of the voltage that must be applied to CG to inject prescribed electrons to the FG.
A semiconductor device in which the confronting areas of the FG and CG of transistor elements are increased is disclosed in xe2x80x9cA 0.24-um2 Cell Process with 0.18-um Width Isolation and 3-D Interpoly Dielectric Films for 1-Gb Flash Memoriesxe2x80x9d (IEEE Tech. Dig. IEDM (1997) pp. 275).
Referring now to FIGS. 1a and 1b, a simple explanation is next presented regarding the semiconductor device described in the above publication. FIG. 1a is a vertical sectional view in which the semiconductor device is cut at the position of a transistor element, and FIG. 1b is a vertical section in which a semiconductor device is cut at a position between transistor elements.
In the interest of simplifying the explanation, the vertical (up-down) and horizontal (right-left) directions are defined in accordance with the figures. Nonvolatile memory 100 that is here taken as an example is provided with semiconductor substrate 101. A plurality of transistor elements 110 are arranged as memory cells on semiconductor substrate 101 in a matrix form in the horizontal direction of the figure and in the direction of depth of the figure.
Transistor elements 110 are separated in the horizontal direction at element separators 102, element separators 102 having their lower portions buried in the surface of semiconductor substrate 101 and their upper portions protruding from the surface of semiconductor substrate 101. Source regions 111 and drain regions 112 are formed below the level of the surface of semiconductor substrate 101 at the positions of the transistor elements 110 that are separated by element separators 102, and gate dielectric film 113 is formed on the surface of semiconductor substrate 101.
Lower FG 114 are formed on the surface of this gate dielectric film 113 at positions between source regions 111 and drain regions 112, and upper FG 115 are formed on the surface of lower FG 114. Source regions 111 and drain regions 112 are formed in the direction of depth of the figure, but lower FG 114 and upper FG 115 are divided into a plurality of sections in the direction of depth of the figure, thereby realizing a configuration in which a plurality of transistor elements 110 are arranged in the direction of depth of the figure.
Interlayer dielectric film 103 is formed between element separators 102 and each of FG 114 and 115. Upper FG 115 are formed to spread over the surface of interlayer dielectric film 103 with the area of the upper surface of upper FG 115 being greater than the area of lower FG 114. CG 117 is formed across the horizontal direction of the figure on the upper surface of these upper FG 115, with ONO (Oxide-Nitride-Oxide) film 116, which is an intergate dielectric film, interposed.
The upper surface of this CG 117 and the uppermost surface of the above-described configuration formed on semiconductor substrate 101 are protected by isolation layer 104. In this nonvolatile memory 100, CG 117 function as word lines and drain regions 112 function as bit lines.
In nonvolatile memory 100 of the above-described configuration, each of a multiplicity of transistor elements 110 arranged in matrix form can store individual bits of data as a memory cell, and moreover, can erase the stored data for prescribed units of a plurality of transistor elements 110.
In a case in which one part of binary data is written to a particular transistor element 110, electrons are injected to FG 114 and 115 by applying 0 V to source region 111, 0 V to drain region 112, and a voltage of 18 V to CG 117.
In transistor element 110 in which data are not written at this time, either a voltage of 0 V is applied to CG 117, or a voltage of 5 V is applied to drain region 112 and source region 111 is made open, whereby the electric field that works on gate dielectric film 113 remains weak and electrons are not injected in FG 114 and 115.
In a transistor element 110 in which electrons are not injected into these FG 114 and 115, the cell threshold value is kept at a prescribed erase level, and stored data are therefore maintained at a default value of xe2x80x9c0.xe2x80x9d In transistor element 110 in which electrons are injected to FG 114 and 115, on the other hand, the cell threshold value becomes a prescribed write level, whereby, for example, the data xe2x80x9c1xe2x80x9d are stored.
In above-described nonvolatile memory 100, the FG is of a two-layered construction of lower FG 114 and upper FG 115, and CG 117 confronts upper FG 115 without confronting lower FG 114. Since the upper surface of this upper FG 115 both extends horizontally and is formed with a concave center, CG 117 confronts upper FG 115 over a large surface area. The capacitance between CG 117 and upper FG 115 is therefore great, thus reducing the voltage that must be applied to CG 117 to control the electrons of FG 114 and 115.
Next, regarding one example of a method of fabricating nonvolatile memory 100 having the above-described configuration, a gate dielectric film and a lower polysilicon film are first grown in that order on the upper surface of semiconductor substrate 101. Gate dielectric film 113 and lower FG 114 are next formed by removing portions of lower polysilicon film and gate dielectric film so as to divide the lower polysilicon film into a plurality of sections in the horizontal direction.
Source region 111 and drain region 112 are next formed by ion-injecting impurities into semiconductor substrate 101, and interlayer dielectric film 103 is grown on the surfaces of this semiconductor substrate 101 and lower FG 114. A trench is formed and insulating material embedded at the position of element isolator 102 of this interlayer dielectric film 103, and the upper surface of interlayer dielectric film 103 is leveled by CMP (Chemical Mechanical Polishing).
Next, after forming a trench in the surface of lower FG 114, an upper polysilicon film is formed, and upper FG 115 are formed by removing portions of the upper polysilicon film so as to divide this upper polysilicon film into a plurality of sections. ONO film 116 is then formed on the surface of this upper FG 115, and an upper conductive film is grown from polysilicon film or tungsten silicide on this surface.
For the purpose of dividing transistor element 110 in the direction of depth of the figure, a photoresist is first applied to the surface of the upper conductive film, a resist mask is formed by patterning this photoresist, and CG 117 is formed by etching the upper conductive film using this resist mask as shown in FIG. 1a. 
Next, the etching gas is altered with the resist mask left in the regions between transistor elements 110 in the direction of depth of the figure, and ONO film 116 is then subjected to anisotropic etching, following which the etching gas is again altered, and transistor elements 110 are separated in the direction of depth of the figure by etching both upper FG 115 and lower FG 114.
In nonvolatile memory 100 as described in the foregoing explanation, CG 117 and upper FG 115 have a high capacitance because the confronting areas of upper FG 115 and CG 117 are large, thereby allowing a reduction in the voltage that is applied when writing data. However, difficulties can be expected when fabricating nonvolatile memory 100 of the above-described configuration.
Specifically, in actual nonvolatile memory 100, FG 114 and 115, ONO film 116, and CG 117 must be divided in the direction of depth in order to arrange a plurality of transistor elements 110 in the direction of depth of the figure. Although this can be accomplished by anisotropic plasma etching from above as described hereinabove, ONO film 116 will remain on the side walls of upper FG 115 as shown in FIG. 2a when the surface of upper FG 115 is formed as a depression.
Thus, when the remaining ONO film 116 is completely removed by anisotropic plasma etching from above, etching of ONO film 116 in the horizontal direction will be excessive, with etching proceeding as far as upper FG 115.
Since overetching to completely eliminate the remaining ONO film 116 is therefore not possible, ONO film 116 is under-etched. As a result, portions of FG 114 and 115 remain as shown in FIG. 2b and FIG. 3, and adjacent transistor elements 110 in the direction of depth will short circuit with each other.
In such cases, a write voltage or erase voltage to a particular transistor element 110 will affect adjacent transistor elements 110 and thus cause malfunctions in which erroneous data are written to transistor elements 110 that cannot be predicted or in which written data are erased.
One possible method of solving this problem involves carrying out plasma etching until portions of ONO film 116 that are attached in the vertical direction are eliminated, but this method results in excessive etching in which areas not requiring etching are etched.
It is an object of the present invention to provide a semiconductor device that can be easily fabricated wherein the FG of transistor elements that are arranged in matrix form are provided in two layers and the area that confronts CG is increased, as well as a method of fabricating such a semiconductor device.
The semiconductor device of the present invention has a configuration in which a gate dielectric film is formed on the surface of a semiconductor substrate having source regions and drain regions, a plurality of FG are formed on the gate dielectric film, a plurality of intergate dielectric films are formed on the FG, and a plurality CG are formed on the intergate dielectric films. Mounds are formed on both sides of FG. Interlayer dielectric films are formed between the gate dielectric films and intergate dielectric films and covering these mounds. The FG are constituted by upper FG and lower FG, the upper FG being formed to spread toward the areas in which the mounds are formed and cover a portion of the interlayer dielectric film. The gate dielectric film is formed in a shape that does not rise in a direction that is substantially perpendicular to the surface of the semiconductor substrate at least above the upper FG.
The source regions and drain regions are formed to extend in one direction along the surface of the semiconductor substrate. The plurality of FG are arranged in the direction in which the source regions and drain regions extend, whereby a plurality of transistor elements are arranged in the direction in which the source regions and drain regions extend between the portions in which the source regions are formed and the portions in which the drain regions are formed.
By configuring the semiconductor device as described above, the area of the upper surfaces of the upper FG, i.e., the area that confronts CG, is greater than the area of the upper surfaces of the lower FG. The capacitance between the CG and upper FG is therefore increased, and the voltage that is applied to CG for controlling the electrons of the FG can be reduced.
The semiconductor device of the above-described invention has a configuration in which a plurality of transistor elements are arranged in the direction in which the source regions and drain regions extend. When forming such a construction, a method is adopted in which upper FG, intergate dielectric films, and CG are formed on the lower FG in the direction in which the source regions and drain regions extend, following which these components are subjected to partial etching to divide into a plurality of sections in the direction in which the source regions and drain regions are formed. Here, the intergate dielectric film is formed in a shape that does not rise in a direction that is substantially perpendicular to the surface of the semiconductor substrate at least above the upper FG, and as a result, no intergate dielectric film is left by etching.
According to a preferable embodiment of the semiconductor device of the present invention, in order to form the intergate dielectric film in the above-described shape, the surfaces of the upper FG are formed in a shape having no portions that are substantially perpendicular to the surface of the semiconductor substrate. Furthermore, according to a preferable embodiment of the semiconductor device of the present invention, in order to form the surface of the upper FG in the above-described shape, the surface of the interlayer dielectric film is formed in a shape having no portions that are substantially perpendicular to the surface of the semiconductor substrate.
In addition, according to a preferable embodiment of the semiconductor device of the present invention, a plurality of the above-described transistor elements are also arranged in a direction that is perpendicular to the direction in which the source regions and drain regions extend. In this case, the mounds that are formed at both sides of the lower FG also function as element isolation electrodes that insulate transistor elements that are adjacent in the direction that is perpendicular to the direction in which the source regions and drain regions extend. In this case, moreover, the element isolation electrodes are preferably formed from the same material as the lower FG. Element isolation transistors are thus formed from the element isolation electrodes, drain regions, and source regions. In this case, moreover, the element isolation electrodes and semiconductor substrate may be grounded. Since the element isolation transistors are kept in an OFF state, transistor elements that are adjacent in the direction that is perpendicular to the direction in which the source regions and drain regions extend are insulated.
The method of fabricating the semiconductor device of this invention is a method of fabricating a semiconductor device having a configuration in which a plurality of transistor elements are arranged along the direction in which the source regions and drain regions extend, this method having as its most characteristic step a step for forming the interlayer dielectric film, upon which the upper conductive layer that constitutes the upper FG of the transistor elements is formed, in a shape in which the surface of the interlayer dielectric film is not substantially perpendicular to the surface of the semiconductor substrate at both sides of a lower conductive layer that constitutes the lower FG of the transistor elements.
Thus, despite forming an upper conductive layer on the interlayer dielectric film, and further, despite forming an intergate dielectric film on this upper conductive layer, the surface of the intergate dielectric film is also formed in a shape having no portions that are substantially perpendicular to the surface of the semiconductor substrate in regions in which the transistor elements of the semiconductor substrate are formed. Accordingly, upper conductive layer, intergate dielectric film, and a control conductive layer, which is to become the CG, are formed on the lower conductive layer; and when these layers and film are subjected to partial etching to divide into a plurality of sections in the direction in which the source regions and drain regions extend, none of intergate dielectric film is left behind by etching.
In a preferable embodiment of the method of fabricating a semiconductor device of the present invention, a base conductive layer is formed over the entire surface of the gate dielectric film after forming the gate dielectric film, and the lower conductive layer and mounds are formed by patterning this base conductive layer. The lower conductive layer and mounds are thus simultaneously formed of the same material.
Further, in a preferable embodiment of the method of fabricating a semiconductor device of the present invention, the step of forming an interlayer dielectric film includes steps of: forming a lower interlayer dielectric film on the surface of the semiconductor substrate to cover the gate dielectric film, mounds, and lower conductive layer; etching the areas of the lower interlayer dielectric film that are between mounds to expose at least the upper surface of the lower conductive layer; forming an upper interlayer dielectric film on the surface of the semiconductor substrate, thereby covering the exposed lower conductive layer and interlayer dielectric film; and etching back the upper and lower interlayer dielectric films to expose the upper surface of the lower conductive layer.
In this case, the film thickness of the interlayer dielectric film that is removed by etching of the upper and lower interlayer dielectric film in the step of exposing the upper surface of the lower conductive layer is preferably set according to the width of etching between the mounds in the step of etching the areas of the lower interlayer dielectric film that are between mounds to expose at least the upper surface of the lower conductive layer. The relation between the etching width and the film thickness of the removed interlayer dielectric film is thus set as appropriate, and the interlayer dielectric film can be formed such that the surface of the interlayer dielectric film is not substantially perpendicular to the surface of the semiconductor substrate at both sides of the lower conductive layer despite exposing the upper surface of the lower conductive layer.
In an actual case, the interlayer dielectric film is formed so as to satisfy the relations:
axe2x89xa7b+2c+d
axe2x89xa6exe2x88x92d
where a is the etching width, b is the width of the upper surface of the lower conductive layer, c is the thickness of the interlayer dielectric film that is removed by etchback in the step of exposing the upper surface of the lower conductive layer, d is the maximum positional error in the direction of width of the lower conductive layer when etching the areas between mounds, and e is the spacing between adjacent mounds.
In a preferable embodiment of the method of fabricating a semiconductor device of the present invention, in the step of forming the lower conductive layer, the step of forming the upper conductive layer, and the step of forming the interlayer dielectric film, the thickness of the lower conductive layer, the thickness of the upper conductive layer, and the thickness of the interlayer dielectric film are set such that damage does not occur to the mounds when partially etching the control conductive layer, the intergate dielectric film, the upper conductive layer, and the lower conductive layer in the step of forming the plurality of transistor elements.
Finally, in the description in this specification, expressions such as xe2x80x9cleftxe2x80x9d, xe2x80x9crightxe2x80x9d, xe2x80x9chorizontal directionxe2x80x9d and xe2x80x9cdirection of depthxe2x80x9d are used with the figures as a reference for the sake of convenience to describe, for example, the direction of arrangement of each of the constituent elements on the semiconductor substrate. However, these expressions do not represent absolute directions of an actual device at the time of fabrication or at the time of use of the device. Particularly, the directions xe2x80x9chorizontalxe2x80x9d and xe2x80x9cdepthxe2x80x9d represent directions that are mutually orthogonal within a plane that is parallel to the surface of the substrate, which is the main structure of the semiconductor device of the present invention. Further, the directions xe2x80x9cupxe2x80x9d, xe2x80x9cdownxe2x80x9d, and xe2x80x9cverticalxe2x80x9d similarly represent directions that are perpendicular to the surface of the substrate, and do not indicate absolute directions of the actual device at the time of fabrication or at the time of use of the device.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.